The present invention relates to a semiconductor device and a method of producing the semiconductor device. In particular, the present invention relates to a semiconductor device, in which a contact plug has a specific configuration so that a contact resistivity does not increase even through a shift in an alignment occurs when a contact hole is formed.
As a conventional semiconductor device, a semiconductor non-volatile memory having memory cells arranged in a matrix pattern has been proposed (refer to Patent Reference). Patent Reference: Japanese Patent Publication No. 2004-343015
A configuration of the conventional semiconductor non-volatile memory disclosed in Patent Reference will be explained with reference to FIG. 14 and FIGS. 15(A) to 15(C). FIG. 14 is a schematic view showing the configuration of the conventional semiconductor non-volatile memory having memory cells 15 arranged in a matrix pattern.
FIGS. 15(A) to 15(C) are schematic sectional views showing the conventional semiconductor non-volatile memory. More specifically, FIG. 15(A) is a sectional view thereof taken along a line 15(A)-15(A) in FIG. 14, FIG. 15(B) is a sectional view thereof taken along a line 15(B)-15(B) in FIG. 14, and FIG. 14(C) is a sectional view thereof taken along a line 15(C)-15(C) in FIG. 14.
In the conventional semiconductor non-volatile memory, active areas (AC) 29b, and gate electrodes (CG) 34 are arranged to cross with each other in a matrix pattern. Each of the active areas 29b, has a rectangular shape with a longitudinal direction thereof aligned with a column direction of the matrix pattern, and each of the gate electrodes 34 has a rectangular shape with a longitudinal direction thereof aligned with a row direction of the matrix pattern. Further, the active areas 29b are separated with element separation areas 29a, extending in the column direction.
Each of the memory cells 15 is a so-called sidewall type memory, in which sidewall portions 50 capable of accumulating electric charges are disposed to sandwich the gate electrode of an MOS (Metal Oxide Semiconductor) type field effect transistor. The sidewall portion 50 has a laminated structure capable of accumulating electric charges, in which a lower insulation film 52, an electric charge accumulation film 54, an upper insulation film 56, and a sidewall nitride film 58 are laminated in this order.
In the conventional semiconductor non-volatile memory, the gate electrodes 34 extend along the row direction. With the configuration described above, the memory cells 15 arranged in the column direction adjacent to with each other share an impurity diffused area functioning as a source-drain. Accordingly, it is not necessary to provide an element separation area between the memory cells 15 arranged in the column direction adjacent to with each other, thereby reducing an element forming area.
In the memory cells 15 arranged in the row direction adjacent to with each other, impurity diffused areas 40 thereof are electrically connected to one bit line through a conductive plug or cell contact 162 having an oval column shape. Accordingly, it is not necessary to provide a wiring portion for connecting the impurity diffused areas 40 of the memory cells 15 arranged in the row direction adjacent to with each other, thereby reducing an element forming area. The conductive plug 162 includes a titanium film 164, a titanium nitride film 166, and a tungsten conductive member 168.
Further, with the configuration described above, it is possible to produce the cell contacts (CC) 162 along the column direction in a self-compatible manner. Accordingly, it is possible to minimize a variation in a property due to an alignment of the cell contacts (CC) 162 with respect to the gate electrodes (CG) 34 (referred to as a CC-CG alignment). As a result, it is not necessary to provide a margin for the CC-CG alignment, thereby reducing an element forming area.
In the configuration described above, however, a resistivity of the cell contact 162 may increase or cause a variation in a resistivity thereof due to a shift in the alignment of the cell contacts (CC) 162 with respect to the active areas (AC) 29b, (referred to as a CC-AC alignment).
With reference to FIG. 16, the resistivity of the cell contact 162 (referred to as a contact resistivity) will be explained in a case that the shift in the CC-AC alignment occurs. FIG. 16 is a schematic sectional view showing the conventional semiconductor non-volatile memory for explaining the shift in the CC-AC alignment.
When the shift in the CC-AC alignment occurs, an area of a semiconductor substrate exposed at a bottom surface of a contact hole 61 decreases upon forming the cell contact 162. Accordingly, when a metal silicide film 146 is formed in a later step, an area of the metal silicide film 146 having a low resistivity also decreases. When the area of the metal silicide film 146 decreases, the contact resistivity increases.
When the contact resistivity increases, it may be difficult to apply a sufficient voltage to a drain upon wiring the memory cell 15, thereby causing a decrease in a writing speed or a writing error. Further, when reading out from the memory cell 15, it is difficult to supply a sufficient voltage to the drain, thereby causing a reading error.
In view of the problems described above, an object of the present invention is to provide a semiconductor device and a method of producing the semiconductor device capable of solving the problems of the conventional semiconductor device. In the semiconductor device, it is possible to prevent a contact resistivity from increasing even when a shift in an alignment of a cell contact (CC) with respect to an active area (AC) occurs.
Further objects and advantages of the invention will be apparent from the following description of the invention.